1. Field of the Invention
The present invention is in the field of multi-layer ceramic capacitors, and more particularly relates to a method of making marginless multi-layer ceramic capacitors.
2. The Prior Art
The use of multi-layer ceramic capacitors is progressively increasing. In order to minimize the volume, it is highly desirable that ceramic capacitors have a maximum capacitance per unit area. Additionally, with the high cost of dielectric materials typically employed, e.g. ceramic materials having high dielectric constants, such as titanates, zirconates, stannates of the alkali earth metals, e.g. calcium, barium, strontium, and titanium, it is desirable to minimize the quantity of dielectric material employed.
A further desideratum is that the capacitors fabricated in a given run may be manufactured to have a predetermined desired capacitance value with minimal variations.
The methods heretofore used in the fabrication of multi-layer ceramic capacitors have been deficient in various aspects. More particularly, they have resulted in the production of capacitors having less than optimal capacitance to area ratio. Additionally, as will be more fully set forth hereinafter, the typical practice has been to fabricate capacitors of a value somewhat higher than necessary for a given application and thereafter erode the capacitors while measuring capacitance variations, to reduce the capacitance to a desired lower value.
By way of example, reference is made to U.S. Pat. Nos. 3,456,170 to Hatch and 3,394,386 to Weller.
Obviously, the fabrication of an over-size capacitor and the subsequent erosion thereof are wasteful of materials and labor and also result in the production of a capacitor whose overall dimensions are larger than required.
In accordance with typical manufacturing procedures for multi-layer ceramic capacitors, as exemplified for instance by U.S. Pat. Nos. 3,235,939 to Rodriguez, 3,992,761 to McElroy et al and 4,008,514 to Elderbaum, the prior art methods for manufacturing ceramic capacitors have resulted in the production of over-size capacitors for the reason that such methods involve the imprinting on the ceramic material of a multiplicity of discrete increments of electrode surrounded by uncovered areas or borders of ceramic. Plural sheets bearing the multiple electrode pattern are placed in registry and the resultant stack is punched or otherwise processed to sever capacitor blanks by cuts extending through the borders.
The fabricating method described and resultant product are disadvantageous in many aspects, including the waste of ceramic inherent in providing borders between electrodes and the fact that the overall dimensions of the finished product are enlarged by the size of the border material remaining, and that with a given ceramic body area, the electrode material does not cover the entire area, so that the resultant capacitance is not maximized.
To summarize, the prior art methods used in the fabrication of multi-layer ceramic capacitors have heretofore involved imprinting of relatively large sheets with a multiplicity of discrete electrode patterns, superimposition of such sheets, and severing of the sheets in the margin areas or borders between electrode patterns, thereby providing capacitors which have larger than necessary bulk due to the surrounding ceramic borders, and by reason of such borders do not maximize the possible capacitance of the unit, and for the same reason employ in their fabrication larger than necessary quantities of expensive ceramic material.
Where close electrical tolerances are required, it has been necessary to manufacture the ceramic capacitors oversized and thereafter reduce the capacitance value to achieve a unit having acceptable tolerance levels.